As shown in FIG. 1, a conventional HVIC includes four portions: a low-voltage control circuit, a low-side driver connected to ground, a high-voltage level shifter and a high-side driver. The voltage of the tub shown in this figure can be varied from the voltage of the ground up to the voltage of the bus, which has a high-voltage related to the ground.
In Ref. [1], the BCD techniques are presented for implementing the four circuits shown in the block of FIG. 1. However, DI and JI techniques must be used in BCD techniques. Therefore, the technologies employed are normally incompatible with conventional CMOS and BiCMOS technologies. Furthermore, the areas of the high-voltage devices made by BCD technologies are normally large. As a result, the costs of such HVICs or PICs are high.
In Ref. [2] and [3], the present inventor proposed techniques to implement high-side and low-side high-voltage devices by taking advantage of optimum variation lateral doping. The techniques are CMOS and/or BiCMOS technologically compatible, so that high-side and low-side high voltage devices as well as high-side drivers can be realized on a single chip with lower cost.
However, the lateral power MOSTs, especially the lateral high-side power MOST made by such techniques has a large specific on-resistance. This can be illustrated by FIG. 2, the middle portion of which schematically shows the structure of a high-side n-MOST. When a high voltage related to the substrate is applied on the drain electrode DH, the n-layer of the first surface voltage-sustaining region is depleted in a large extent, remains a small part of it to be neutral. That means it offers a high specific on-resistance.
References related to the prior arts are:    [1] B. Marari, et al., <Smart Power IC's Technologies and Applications>, Springer-Verlag, Berlin, Heidelberg, N.Y., 1995.    [2] X. B. Chen, U.S. Pat. No. 5,726,469 or Chinese patent ZL 95108317.1    [3] X. B. Chen, U.S. Pat. No. 6,310,365 B1 or Chinese Patent, ZL 98116187.1.    [4] X. B. Chen, et al., “Theory of optimum design of reverse-biased p-n junctions using resistive field plate and variation lateral doping”, Solid-State Electronics, Vol. 35, No. 9, pp. 1365–1370 (1992).    [5] X. B. Chen, et al., “Lateral high-voltage devices using an optimized variational lateral doping”, Int. J. Electronics, Vol. 80, No. 3, pp. 449–459 (1996).